1. Field of the Invention
This invention generally relates to computer systems; and more specifically, the invention relates to connections, in computer systems, between controllers, for example memory controllers or intermediate buffer devices, and the addressable devices which they control.
2. Background Art
Contemporary high performance computing main memory systems incorporates memory as an array of DRAM memory devices. A processor communicates a memory request to a memory controller, which in turn activates one or more DRAM devices and then reads (fetches) or writes (stores) the data. The DRAM devices could be directly connected to the memory controller (direct connect), or there may be intermediate buffer chips, registers, or more complicated hub chips (essentially data funnels) between the memory controller and the DRAMs. The DRAMs are often organized on memory modules; the usual arrangement is a dual inline memory module (DIMM), which provides a convenient memory bus and an 8 Byte wide data bus to the memory controller.
High-speed memory systems may be provided with a feature referred to as receiver parallel termination, which dampen reflections from DRAMs in the systems. Such parallel termination can be implemented with a resistor voltage divider, comprised of one resistor from the signal net to the driver and/or receiver supply voltage (Vdd) and a second resistor from the signal net to the ground reference voltage (Gnd). This type of parallel termination is simple to implement but results in significant DC power dissipation due to current flowing directly through the termination resistors from Vdd to Gnd. In order to reduce power consumption, parallel termination is frequently implemented with a push-pull voltage supply 380, which provides a midpoint termination voltage (Vtt) between Vdd and Gnd.
For a multi-bit bus comprised of a number of nets, each of which is parallel terminated to the same Vtt supply, and for a realistic lossy Vtt supply, the total termination power of the bus varies with the difference between the number of nets driven high vs. low. Significant power savings can be obtained by controlling the state to which address and control bits are driven when the address and control bus is inactive.